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Programmable Array Logic
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121	LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-09 02:20:06 Boolean algebra Diagrams Field-programmable gate array Binary decision diagram Lookup table Xilinx Multiplexer Artificial neuron Function Computing Mathematics Electronic engineering
122	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods
123	VLSI DESIGN 1996, Vol. 4, No. 2, pp. i-ii (C[removed]Reprints available directly from the publisher Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-11 09:05:38 Logic design Field-programmable gate array Hindawi Publishing Corporation CPU design Logic simulation Parallel computing Application-specific integrated circuit Digital electronics Simulation Electronic engineering Electronic design automation Integrated circuits
124	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:17:53 Digital electronics Electronic design And-inverter graph Retiming Logic synthesis Algorithm Field-programmable gate array Logic gate Parallel computing Electronic engineering Electronic design automation Formal methods
125	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation
126	Verification of System LSIs for Image Processing  Yoshihiko Hayashi  Noriyuki Ikuma Add to Reading List Source URL: www.fujitsu.com Language: English - Date: 2013-02-06 07:16:32 Hardware emulation Functional verification Logic simulation Verification and validation Field-programmable gate array Application-specific integrated circuit Verification Electronic engineering Digital electronics Systems engineering
127	Magic: An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko Niklas Een Robert Brayton Stephen Jang Maciej Ciesielski Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2010-03-19 22:25:46 Digital electronics Integrated circuits Standard cell Field-programmable gate array Logic optimization Retiming Physical design Logic synthesis Placement Electronic engineering Electronic design automation Electronic design
128	SmartOpt: An Industrial Strength Framework for Logic Synthesis Stephen Jang, Dennis Wu, Mark Jarvin Billy Chan, Kevin Chung Xilinx Inc. {sjang,wudenni,mjarvin,billy,kevinc}@xilinx.com Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-12-17 22:28:43 Digital electronics Integrated circuits Electronic design Field-programmable gate array Xilinx Logic synthesis Application-specific integrated circuit Placement Static timing analysis Electronic engineering Electronics Electronic design automation
129	Paper formatting guidelines for FPL 2005 proceedings Add to Reading List Source URL: www.automatedtrader.net Language: English - Date: 2008-04-02 15:55:41 Field-programmable gate array Monte Carlo methods in finance Parallel computing Logic simulation Monte Carlo method Accelerator Simulation Hardware description language Digital electronics Electronic engineering Logic design
130	Less is more when you design with configurable and combination logic By Daniel Jensen, Regional Marketing Manager, NXP Semiconductors Summary If you’d like to squeeze more functionality into less space, while simplifyi Add to Reading List Source URL: www.nxp.com Language: English - Date: 2014-05-09 04:18:53 Negated AND gate XNOR gate NOR gate OR gate Logic family AND gate Series Programmable Array Logic Logic gates Electronic engineering Electronics